Parallel Computing on Stampede

April 18-19, 2013 (Thursday and Friday)
8:30 a.m. to 5 p.m. CT
ROC 1.900

J.J. Pickle Research Campus
10100 Burnet Rd.
Austin, TX 78758

This class will be webcast.

Registration closes April 12.

The Stampede supercomputer at the Texas Advanced Computing Center went into production in January 2013 and is the first system to deploy at scale the Intel Xeon Phi CoProcessor. Stampede provides nearly 10 petaflops of peak performance, and is the new flagship system of the US National Science Foundation’s XSEDE Cyberinfrastructure.

Stampede provides more than 100,000 cores and 2PF of Intel Xeon E5 “Sandy Bridge” processors, and an additional 7+ PF of Intel Xeon Phi CoProcessors. In this tutorial, we will introduce the Stampede architecture, and cover how to achieve performance using both the conventional processors as well as the coprocessors.

Topics will include:
-Stampede architecture overview
-The Stampede user environment, including the batch system, compiler environment, application modules, etc.
-MPI and OpenMP parallel programming
-Hands-on exercises with Stampede.
-Basic optimization and vector tuning on Stampede for Sandy Bridge and Xeon Phi Coprocessors (MICs)
-Hybrid computing
-Intel Xeon Phi Coprocessor (MIC) overview
-Programming models for Sandy Bridge – MIC computing: native, symmetric and offload.

The labs will be available for remote users. However, we will not be able to assist remote users with problems during the lab. Remote users are invited to submit their questions via email.