Parallel Computing on Stampede

05/04/2015 09:00 - 05/05/2015 17:00 CDT
webcast
Registration
Registration open date
04/13/2015 08:14 CDT
Registration close date
04/29/2015 17:00 CDT
Class size restriction
75 registrants

(27 spots left)

Waitlist

0 registrants

Contact Information
Contact
Jason Allison
Contact phone
512-475-9238
Contact email
jasona@tacc.utexas.edu
Location
Name
Texas Advanced Computing Center
Phone
512-475-9238
URL
https://www.tacc.utexas.edu

The Stampede supercomputer at the Texas Advanced Computing Center went into production in January 2013 and was the first system to deploy at scale the Intel Xeon Phi CoProcessor. Stampede provides nearly 10 petaflops (PF) of peak performance and is the flagship system of the National Science Foundation’s XSEDE program. Stampede provides more than 100,000 cores and 2PF of Intel Xeon E5 “Sandy Bridge” processors and an additional 7+ PF of Intel Xeon Phi coprocessors.

In this tutorial, we will introduce the Stampede architecture, describe the user environment, and discuss optimization techniques for both conventional processors as well as the Xeon Phi coprocessors.

Topics will include:

• Stampede architecture overview.
• Stampede user environment, including the batch system, compiler environment, application modules, etc.
• MPI and OpenMP parallel programming
• Hands-on exercises on Stampede.
• Basic optimization and vector tuning on Stampede for Sandy Bridge and Xeon Phi Coprocessors (MICs)
• Hybrid computing
• Intel Xeon Phi Coprocessor (MIC) overview
• Programming models for Sandy Bridge – MIC computing: native, symmetric and offload.

This session has ended.
Posted: 04/13/2015 13:06 UTC