Course Calendar

Parallel Computing on Stampede

Host Site:

Texas Advanced Computing Center

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The Stampede supercomputer at the Texas Advanced Computing Center went into production in January 2013 and is the first system to deploy at scale the Intel Xeon Phi CoProcessor. Stampede provides nearly 10 petaflops of peak performance, and is the flagship system of the US National Science Foundation’s XSEDE Cyberinfrastructure. Stampede provides more than 100,000 cores and 2PF of Intel Xeon E5 “Sandy Bridge” processors, and an additional 7+ PF of Intel Xeon Phi CoProcessors.

In this tutorial, we will introduce the Stampede architecture, and cover how to achieve performance using both the conventional processors as well as the coprocessors.

Topics will include:

Stampede architecture overview
The Stampede user environment, including the batch system, compiler environment, application modules, etc.
MPI and OpenMP parallel programming
Basic optimization and vector tuning on Stampede for Sandy Bridge and Xeon Phi Coprocessors (MICs)
Hybrid computing
Intel Xeon Phi Coprocessor (MIC) overview
Hands-on exercises with Stampede

More information:


In person (Texas Advanced Computing Center)

10/22/2015 09:00 - 10/23/2015 17:00 CDT (SESSION HAS ENDED)
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Registration CLOSED
Registration open date
10/02/2015 09:00 CDT
Registration close date
10/16/2015 17:00 CDT
Class size restriction
30 registrants

(25 spots left)


0 registrants

Contact Information
Jason Allison
Contact phone
Contact email
Texas Advanced Computing Center
J.J. Pickle Research Campus, Building 196, ROC 1.101
10100 Burnet Road (R8700)
Austin, TX 78758-4497
Posted: 10/02/2015 14:33 UTC