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Sneak Preview: The Stampede Supercomputer and the Intel Xeon Phi Coprocessor

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The Stampede supercomputer at the Texas Advanced Computing Center will become available in early 2013, and will be the first system to deploy at scale the Intel Xeon Phi CoProcessor. Stampede will provide nearly 10 petaflops of peak performance, and become the new flagship system of the US National Science Foundation’s XSEDE Cyberinfrastructure.

Stampede will provide more than 100,000 cores and 2PF of Intel Xeon E5 “Sandy Bridge” processors, and an additional 7+ PF of Intel Xeon Phi CoProcessors. In this 3 hour tutorial, we will introduce the Stampede architecture, and cover how to achieve performance using both the conventional processors as well as the coprocessors. A hands-on section will provide early access to the system, including to the Xeon Phi capability.

*This tutorial will be hosted by Intel in Salt Lake City at the Peery Hotel, within walking distance of the SC12 venue, for those attending the SC12 opening Monday night.

The tutorial will assume that attendees are familiar with the basic concepts of supercomputing, parallel processing, and scientific computing. Attendees should have experience with C/C++ or Fortran, and knowledge of MPI and OpenMP.

Topics will include:
-Stampede architecture overview
-Intel Xeon Phi CoProcessor overview
-Programming models for Stampede, including offload, symmetric, and native modes.
-Performance tuning on Stampede, including vectorization and offload extensions for OpenMP
-Hands-on exercises with Stampede.

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In person (Peery Hotel, Salt Lake City)

11/12/2012 08:00 - 11/12/2012 11:00 MST (SESSION HAS ENDED)
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Registration CLOSED
Registration open date
10/22/2012 09:00 CDT
Registration close date
11/09/2012 09:00 CST
Class size restriction
30 registrants

(6 spots left)


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Contact Information
Dan Stanzione
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Peery Hotel, Salt Lake City
110 West Broadway
Salt Lake City, UT 84101
Posted: 10/23/2012 02:29 UTC