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Parallel Computing on Stampede

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XSEDE Training: Parallel Computing on Stampede Jan. 10-11

January 10-11, 2013 (Thursday and Friday)
8:30 a.m. to 5 p.m. CT

This class will be webcast.

Registration closes January 3.

The Stampede supercomputer at the Texas Advanced Computing Center will become available in early 2013, and will be the first system to deploy at scale the Intel Xeon Phi CoProcessor. Stampede will provide nearly 10 petaflops of peak performance, and become the new flagship system of the US National Science Foundation’s XSEDE Cyberinfrastructure.

Stampede will provide more than 100,000 cores and 2PF of Intel Xeon E5 “Sandy Bridge” processors, and an additional 7+ PF of Intel Xeon Phi CoProcessors. In this tutorial, we will introduce the Stampede architecture, and cover how to achieve performance using both the conventional processors as well as the coprocessors.

The MIC instruction will be the second half of the second day of the class, Friday, January 11.

Topics will include:
-Stampede architecture overview
-The Stampede user environment, including the batch system, compiler environment, application modules, etc.
-MPI and OpenMP parallel programming
-Hands-on exercises with Stampede.
-Basic optimization and vector tuning on Stampede for Sandy Bridge and Xeon Phi Coprocessors (MICs)
-Hybrid computing
-Intel Xeon Phi Coprocessor (MIC) overview
-Programming models for Sandy Bridge – MIC computing: native, symmetric and offload.

The labs will be available for remote users. However, we will not be able to assist remote users with problems during the lab. Remote users are invited to submit their questions via email.

Agenda (Agenda is subject to change)

Day 1 (Thursday, Jan 10, 2013)

Morning (Basics)

08:30-08:45 TACC Overview
08:45-09:45 Introduction to Parallel Computing
09:45-10:00 Break
10:00-11:00 User Environment
11:00-11:30 Lab 1 (User Environment)
11:30-12:30 Lunch

Afternoon (Programming)

12:30-13:50 OpenMP Programming
13:50-14:30 Lab 2 (OpenMP)
14:30-14:45 Break
14:45-16:10 MPI Programming
16:10-17:00 Lab 3 (MPI)

Day 2 (Friday, January 11, 2013)

Morning (Advanced)

08:30-09:30 TACC Systems Review
09:30-10:30 Optimization & Scalability
10:30-10:45 Break
10:45-11:30 Hybrid Computing
11:30-12:00 Lab 4 (Hybrid)
12:00-12:45 Lunch

Afternoon (Coprocessing with MIC)

12:45-13:30 MIC (Xeon Phi Coprocessor)
13:30-14:30 Native Computing (& Optimization)
14:30-14:45 Break
14:45-15:15 Symmetric Computing
15:15-16:15 Offloading
16:15-17:00 Lab 5 (MIC)

More information:



01/10/2013 08:30 - 01/11/2013 17:00 CST (SESSION HAS ENDED)
View Session Details →
Registration CLOSED
Registration open date
10/24/2012 18:54 CDT
Registration close date
01/03/2013 14:00 CST
Class size restriction
200 registrants

(100 spots left)


0 registrants

Contact Information
Bob Garza
Contact phone
Contact email
1.101 J.J. Pickle Research Campus, Building 196
10100 Burnet Road (R8700)
Austin, TX 78758-4497
Posted: 10/24/2012 23:54 UTC